Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled a new of improvements to the Cadence SPB Allegro and OrCAD 17.20 families of products aimed at boosting performance and productivity through improvements features and big fixed issues.

1920958 ADW ADWSERVER Designer server will not start due to corrupt inr file
2039243 ADW LIBIMPORT libimport ignores footprints generated by Library Creator due to changes of attribute names
2113226 ADW PART_MANAGER System Capture stops responding while importing DE-HDL sheets
2035942 ALLEGRO_EDITOR ARTWORK 'Create Artwork' is slow when all films are selected
2096958 ALLEGRO_EDITOR DFA Cannot launch Constraint Manager after assigning CSet and closing
2087181 ALLEGRO_EDITOR DFM DFM reporting false positive hole to hole with stacked microvias
2099400 ALLEGRO_EDITOR DFM Placing a mechanical pin on a cutout causes PCB Editor to crash
2067214 ALLEGRO_EDITOR DRC_CONSTR Constraint Manager crashes for design linked board
2097464 ALLEGRO_EDITOR MULTI_USER Design data lost if network connection drops in Symphony
2108211 ALLEGRO_EDITOR MULTI_USER Error: Update #1 (Perm shape) was rejected by server
2117154 ALLEGRO_EDITOR MULTI_USER Error message needed for Symphony for client disconnections
2100149 ALLEGRO_EDITOR REPORTS Error message (SPMHDX-9) for too many field names while generating dangling via report
2101932 ALLEGRO_EDITOR REPORTS PCB Editor internal error (SPMHDX-9) for too many field names when running BOM report
2111449 ALLEGRO_EDITOR SYMBOL 'Layout - Renumber' results in error
2102177 ALLEGRO_EDITOR UI_GENERAL axlDMBrowsePath returns incomplete information
2105342 ALLEGRO_EDITOR UI_GENERAL PCB Editor stops responding for 'Show Element - Find - Symbol Type' on a particular board
2085443 APD ARTWORK Gerber lacks precision required to void some vias for a design in artwork output: need warning
2080118 CONCEPT_HDL CORE Getting error after adding offpage to bus and assigning a new value to $sig_name
2099438 CONCEPT_HDL CORE Genview allows dragging group of signals in split symbol distribution form
2108289 CONCEPT_HDL CORE Variant data is not in sync with the packaged data
2087217 CONCEPT_HDL OTHER Variant back annotation will not work if there is a double quote (") in the description field of a part
2107430 CONCEPT_HDL PAGE_MGMT Insert page is not working
2063875 CONSTRAINT_MGR OTHER PCB Editor crashes on deleting match group without closing Constraint Manager
2103729 F2B DESIGNVARI Cannot enable hierarchical variants for block
2099076 F2B PACKAGERXL Package fails for 'Save Hierarchy', but succeeds for 'Save'
2081132 INSTALLATION SPB Part Information Manager cannot connect to EDM server after upgrading to HotFix 053
1599964 PSPICE ENVIRONMENT Version Info displays 'OrCAD Version Viewer MFC Application has stopped working'
2045497 PSPICE SIMULATOR 'Illegal Parameter Value in File' error when loading Monte Carlo parameter file
2025997 SCM TABLE Copy-Paste Broken in Physical View
2102652 SCM TABLE Unable to copy the Associated Components Ref Des values to Excel
2054225 SIG_INTEGRITY SIGNOISE Cross Section Editor bug after changing the impedance value in Analyze - Preferences
2100075 SIP_LAYOUT DIE_ABSTRACT_ Refresh co-design die running slow
2106312 SIP_LAYOUT DIE_ABSTRACT_ Die abstract I/F to bring into SiP Layout and OrbitIO power/ground and signals not designated as RDL
2106314 SIP_LAYOUT INTERACTIVE Large design causing severe lag in Windows Server machine
2101622 SIP_LAYOUT MULTI_USER Symphony Server rejects the slide commands when tapered trace option is on
2107897 SIP_LAYOUT WIREBOND Design stops responding when running Wire Bond Auto Spread in HotFix 055
2104885 SIP_LAYOUT WLP Advanced WLP: Metal Density Scan, scan area in report is incorrect

About SPB Allegro and OrCAD 17.20-2016. Cadence Design Systems announced new capabilities for OrCAD Capture, PSpice Designer and PCB Designer 17.2-2016 that address challenges with flex and rigid-flex design as well as mixed-signal simulation complexities in IoT, wearables and wireless mobile devices. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.

This OrCAD portfolio includes new advanced technology enabled for integrated rigid-flex planning, design and real-time visualization, as well as built-in translators that enable direct design imports from select EDA vendors. PSpice Designer now supports system-level simulation using C/C++/SystemC and VerilogA, via the new PSpice compact model interface. This enables hardware/software virtual prototyping so that electrical engineers can design and simulate intelligent IoT devices. OrCAD is the only fully scalable PCB design solution available in the market that seamlessly transitions from mainstream to enterprise PCB solution with the Allegro environment.

To enable a faster and more efficient flex and rigid-flex design creation critical to IoT, wearables and wireless devices, the OrCAD portfolio uses a new multi-stack-up database capability and extensive in-design inter-layer checks, which helps users avoid errors introduced through manual checking. The OrCAD portfolio also features enhancements targeted towards improving PCB editors' productivity and ease-of-use in padstack editing, constraint management, shape editing and in-design DRCs. To address efficiency needs, the portfolio includes an advanced design differencing engine that enables design review with global teams using state of art visuals. Finally, to give designers more control over their design component annotation process, advanced annotation and auto-referencing capabilities are now available.

Allegro 17.2 release introduces many new capabilities for Flex and Rigid-Flex designs.

About Cadence. Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.

Product: Cadence SPB Allegro and OrCAD (Including EDM)
Version: 17.20.000-2016 HF057
Supported Architectures: x64
Website Home Page :
Language: english
System Requirements: PC
Supported Operating Systems: Windows 7even or newer / 2008 Server R2 / 2012 Server
System Requirements: Cadence SPB Allegro and OrCAD (Including EDM) version 17.20.000-2016 and above
Size: 3.8 Gb